USB VCP printf function

void usb_printf (const char* format,…)
//uint32_t length;
va_list args;
va_start(args, format);
vsnprintf((char *)usbTxBuf, sizeof(usbTxBuf), (char *)format, args);
CDC_Transmit_FS((uint8_t *)usbTxBuf, strlen(usbTxBuf));


STM32F4xx SPI configuration

Concerning SCK clock signal, the user has to respect fixed clock phase and polarity
between communicating nodes. Four possible timing relationships may be chosen by
software, using CPOL (clock polarity) and CPHA (clock phase) parameters.
The CPOL parameter controls the steady state value of the clock when no data is being
transferred. This parameter affects both master and slave modes. If CPOL is low, the SCK
pin has a low-level idle state. If CPOL is high, the SCK pin has a high-level idle state.
If the CPHA parameter is configured as 1EDGE, the first edge on the SCK pin (rising edge if
CPOL is low, falling edge if CPOL is high) is the MSBit capture strobe. Data are latched on
the occurrence of the first clock transition.

If the CPHA parameter is configured as 2EDGE, the second edge on the SCK pin (rising
edge if CPOL is high, falling edge if CPOL is low) is the MSBit capture strobe. Data are
latched on the occurrence of the second clock transition.
The combination of the CPOL and CPHA parameter selects the data capture clock edge
(see Table 2).

Figure 2 shows an SPI transfer with the four combinations of the CPHA and CPOL. The
diagram may be interpreted as a master or slave timing diagram where the SCK pin, the
MISO pin, the MOSI pins are directly connected between the master and the slave device.


Benchmarking Raspberry Pi GPIO Speed

Method and Summary of Results

The basic test setup was to toggle one of the GPIO pins between zero and one as fast as possible. GPIO 4 was selected due to easy access and no overlapping functionality. This is basically the “upper limit” for any signalling one can hope to achieve with the GPIO pins – real-life scenarios where processing needs to be done would need to aim for some fraction of these values. Here are the current results:

Language Library Tested / version Square wave
Shell /proc/mem access 2015-02-14 2.8 kHz
Shell / gpio utility WiringPi gpio utility 2015-02-15 / 2.25 40 Hz
Python RPi.GPIO 2015-02-15 / 0.5.10 70 kHz
Python wiringpi2 bindings 2015-02-15 / latest github 28 kHz
Ruby wiringpi bindings 2015-02-15 / latest gem (1.1.0) 21 kHz
C Native library 2015-02-15 / latest RaspPi wiki code 22 MHz
C BCM 2835 2015-02-15 / 1.38 5.4 MHz
C wiringPi 2015-02-15 / 2.25 4.1 – 4.6 MHz
Perl BCM 2835 2015-02-15 / 1.9 48 kHz



C queue with struct


#define MAX_LEN_PARAMS 10
struct Command
char id;
char length;
char params[MAX_LEN_PARAMS];
char checksum;

struct CommandQueue
struct Command data;
struct CommandQueue *next;

// Two glboal variables to store address of front and rear nodes.
static CommandQueue *front = NULL;
static CommandQueue *rear = NULL;

void cmd_enqueue (struct Command cmd)
struct CommandQueue *q = (struct CommandQueue*)malloc (sizeof (struct CommandQueue));
q->data = cmd;
q->next = NULL;
if (front == NULL && rear == NULL)
front = rear = q;
rear->next = q;
rear = q;

void cmd_dequeue ()
struct CommandQueue *temp = front;
if (front == NULL)
printf (“ERROR: the queue is emprt\r\n");
if (front == rear)
front = rear = NULL;
front = front->next;
free (temp);

struct Command cmd_front ()
if (front == NULL)
struct Command ce; = 255;
printf (“ERROR: queue is empty");
return ce;
return front->data;

void cmd_print ()
struct CommandQueue *temp = front;
while (temp != NULL)
printf (“%d “, temp->;
temp = temp->next;
printf (“\r\n");

int main (void)
struct Command c1; = 1;

struct Command c2; = 2;

struct Command c3; = 3;

struct Command c4; = 4;

struct Command c5; = 5;

cmd_enqueue (c1); cmd_print();
cmd_enqueue (c2); cmd_print();
cmd_enqueue (c3); cmd_print();
struct Command cc1 = cmd_front();
printf (“cc1 id=%d\r\n",;
cmd_enqueue (c5); cmd_print();
return 1;

ARM Interrupt Latency

ARM Interrupt Latency

The interrupt latency of all of the Cortex-M processors is extremely low. The latency count is listed in table 1, and is the exact number of cycles from the assertion of the interrupt request up to the cycle where the first instruction of the interrupt handler is ready to be expected, in a system with zero wait state memory systems:

Processors Cycles with zero wait state memory
Cortex-M0 16
Cortex-M0+ 15
Cortex-M3 12
Cortex-M4 12
Table 1: Interrupt latency of Cortex-M processors with zero wait state memory systems





HAL printf function

by default HAL not override the printf() function, the following code re-direct the printf() to usart.

#ifdef __GNUC__
/* With GCC/RAISONANCE, small printf (option LD Linker->Libraries->Small printf
set to ‘Yes’) calls __io_putchar() */
#define PUTCHAR_PROTOTYPE int __io_putchar(int ch)
#define PUTCHAR_PROTOTYPE int fputc(int ch, FILE *f)
#endif /* __GNUC__ */

* @brief Retargets the C library printf function to the USART.
* @param None
* @retval None
/* Place your implementation of fputc here */
/* e.g. write a character to the USART */
HAL_UART_Transmit(&huart1, (uint8_t *)&ch, 1, 100);
return ch;